Modem integrated circuits (ICs) have different types of input/output (IO) interfaces to communicate with other integrated circuits. The interfaces often have different power supply voltage levels, such as 5V, 3.3V, 2.5V, 1.8V, and 1.2V to support a number of different peripheral devices. This voltage range is broken down into two main categories, high voltage (2.5V-5V and higher), and low voltage (1.2V-1.8V). Most modem transistors, such as those made to present process scales on the order of 45-65 nm processes, are capable of withstanding only low voltage supply levels (1.2V to 1.8V). Accommodating the entire possible range of supply voltages from high voltage (3.3V-5V) to low voltage (1.2V-1.8V) within a single IC represents a significant design and manufacturing challenge, as such voltages must be properly distributed and buffered within the IC to ensure proper operation and protection of the transistors within the device.
An IC can be severely damaged or destroyed when subjected to a voltage that is higher than the design voltage of the integrated circuit. Such high voltages may be due to different power supply levels, or spurious effects, such as Electrostatic Discharge (ESD) events. In general, higher supply voltage levels require the use of thick gate oxide CMOS transistors, but lower stress voltage devices may still required to be used for such higher supply levels. For example, a 3.3V device can be used for a 5V IO interface, and a 2.5V, 1.8V or even 1.2V device can be used for a 3V or 2.5V IO interface. Thus, during normal operation, ICs should be designed to accommodate relatively high supply voltage levels.
Besides potential high voltage exposure during normal operation, all ICs must be protected from ESD effects, since the potential for exposure to such high voltage discharge is ever-present. ESD can originate from sources such as storage bags, device carriers, machinery, host devices, and people. Such sources can easily generate a voltage that is many times greater than the design voltage of an IC. For example, the typical human body can supply an electrostatic discharge of up to 6 KV (kilovolts), as compared to the standard operating voltage for an IC of 5 V or less.
To protect the internal circuitry of an IC from high voltage or ESD events, protection circuits are utilized, such as between the internal circuitry and the IO pins of the IC. Present protection circuits typically utilize reverse-biased diodes acting as avalanche breakdown clamps to limit the voltage between the power supply terminals of the IC. A problem associated with this approach is that the breakdown voltage of the diode can vary widely depending on design and fabrication variations. With advances in process technology, devices become ever smaller, and consequently, have ever lower electrostatic discharge (ESD) break down voltages.
One mechanism that can cause circuit failures during ESD events is a phenomenon known as bipolar snapback. During bipolar snapback, a parasitic bipolar device can conduct large amounts of ESD discharge current by means of a self-biased mechanism through the inherent substrate resistance of the device. Many CMOS devices utilize stacked snapback NMOS structures for ESD protection. These generally work adequately during pulsed ESD operation but experience difficulties at continuous excessive currents or very high currents. A typical NMOS snapback device includes a gate defined by a poly layer, a drain in the form of an n+ region and silicide, and a source. NMOS snapback structures operate using strong avalanche multiplication of charge carriers to create conductivity modulation in the on-state.
Devices utilizing advanced CMOS process technology suffer from the fact that the transistors have less breakdown voltage to protect against ESD. Typically, the stacked snapback voltage has breakdown voltage of about 10V. Such present stacked NMOS snapback devices cannot efficiently protect the device robustly enough from ESD, even in 100 nm technology.